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IR3519
PARAMETER
LGATE low to UGATE high
TEST CONDITION
BOOT = VDD = 7V, PH =0V GND
MIN
5
TYP
15
MAX
UNIT
ns
delay
= 0V, measure time from LGATE
falling to 1V to UGATE rising to
1V.
UGATE low to LGATE high
BOOT = VDD = 7V, PH =0V GND
5
15
ns
delay
= 0V, measure time from UGATE
falling to 1V to LGATE rising to
1V.
Minimum Pulse Width
Passive Gate Pull-Down
Note 1
30
20
50
ns
k ?
Resistance
PH Bias Current
Measure with PWM=Tri-state,
PH=1V
-2
-10
μ A
VDD Under Voltage Lockout Comparator (V UVLO )
Start Threshold
Stop Threshold
Hysteresis Start – Stop
5.65
5.4
6.0
5.7
6.3
6.1
0.4
V
V
V
PWM Input
UGATE Threshold Voltage,
PWM rising
2.0
2.2
2.4
V
V UGATE TH
UGATE Threshold Voltage,
PWM falling
1.9
2.1
2.3
V
V UGATE TH
UGATE Threshold
30
90
170
mV
Hysteresis
LGATE Threshold Voltage,
PWM falling
0.6
0.8
1.0
V
V LGATE TH
LGATE Threshold Voltage,
PWM rising
0.74
0.9
1.1
V
V LGATE TH
LGATE Threshold Hysteresis
Tri-State Bias voltage,
30
1.2
90
1.6
170
1.8
mV
V
V PWM TRI
Input Bias Current V(PWM) = 0V
V(PWM) = 3.3V
V(PWM) = 5V
Tri-State Time Constant C PWM = 20pF, Measure time from
V(PWM) = 0V release to LGATE
-260
140
370
-210
200
460
190
-160
270
570
μ A
μ A
μ A
ns
< 1V. Note 1
C PWM = 20pF, Measure time from
V(PWM) = 3.3V release to
HGATE < 1V. Note 1
C PWM = 20pF, Measure time from
V(PWM) = 5V release to HGATE
< 1V. Note 1
270
380
ns
ns
Page 3 of 10
www.irf.com
8/15/08
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